LVCMOS Based Low Power Implementation of DES Encryption Algorithm on 28nm FPGA

The main objective of Input/Output (IO) standard is to match the impedance of input and output port along with FPGA device. During our research, we observe that different IO standards is taking different power but functionality of Security Algorithm is same with different IO Standard. In this work of hardware security, we are using different varieties of Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) IO Standards available on 7-Series FPGA. We have taken HDL Code of DES Algorithm and implementing on 7-Series FPGA. We are able to reduce the power consumption by 86.07% if we are using LVCMOS12 in place of LVCMOS33. Here, 12, 15, 18, 25, 33 suffix with LVCMOS means 1.2 V, 1.5 V. 1.8 V, 2.5 V and 3.3 V respectively.