On Legalization of Die Bonding Bumps and Pads for 3-D ICs

As state-of-the-art 3-D IC place-and-route flows were designed with older technology nodes and aggressive bonding pitch assumptions, they introduce an unacceptable number of 3-D via overlap violations during routing in real-world scenarios. Specifically, when dealing with higher via pitch to wire size ratios using more advanced technology nodes than they were designed for, these flows struggle to comply with width and spacing rules. In this article, we propose a novel 3-D via legalization stage and a subsequent refinement stage during routing to address this issue. Two independent via legalization methods are introduced: a force-based algorithm and a bipartite-matching algorithm with Bayesian optimization. Our two legalization methods, along with the refinement stage, are compatible with various process nodes, bonding technologies, and partitioning styles. By implementing the modified 3-D routing with the proposed legalizers, we successfully eliminate all 3-D via overlap violations while minimizing the impact on performance, power, or area.