Area-efficient hardware parallelization of neural network CD equalizers for 4×200 Gb/s PAM4 CWDM4 systems

We compare hardware parallelization of CD equalizers on 10 km 4x200 Gb/s IM/DD PAM4 O-band measurements. A single neural network equalizer with multiple output symbols saves 20% of reference chip area versus multiple single-symbol output variants and 77% versus Volterra non-linear equalizers. Multi-task learning enables cost-efficient scenario flexibility.