4×130 Gbit/s PS-PAM-16 transmissions using an integrated SOA-PIN design for intra-DCIs enabled by machine learning

This paper reports the first experimental demonstration of 4×130 Gbit/s probabilistically shaped PAM-16 transmission over 1km using an integrated SOA-PIN design for next-generation intra-DCIs. With a T-spaced neural network equalizer, a BER below the SD-FEC threshold is achieved under a 20-GHz bandwidth limit.