A High Performance and Low Power Subthreshold Voltage Level Shifter Design

A fundamental component within System-on-Chip (SoC) architecture, a level shifter circuit serves as a crucial element in scenarios characterized by the coexistence of multiple power domains on a single chip. Its primary role revolves around the need to convert logic signals spanning diverse voltage levels. This process, often referred to as voltage level translation or logic-level shifting, is pivotal to ensure harmonious interaction across components that demand disparate voltage thresholds. The function of level shifters becomes particularly indispensable when integrating Integrated Circuits (ICs) that inherently require distinct voltage levels for operation. This paper introduces an innovative and novel design for a voltage level shifter, meticulously crafted to proficiently perform the conversion of voltage signals spanning from the subthreshold to the super-threshold region, all the while minimizing propagation latency. Central to this proposal is the incorporation of the standard current mirror topology, augmented with novel features that are tailored to address the shortcomings posed by the conventional current mirror level shifter circuit. The most notable limitation confronted in the traditional setup is the presence of static current when the input signal assumes a high state. The introduced circuit underwent thorough simulation across various CMOS technologies, spanning the realms of 45nm, 65nm, 90nm, and 180nm. The findings reveal a substantial enhancement in propagation delay, standing at an impressive 77.42% improvement when compared to recent designs specifically in the context of90nm CMOS technology. Additionally, the proposed technique excels in corner analysis, outperforming recently reported approaches in this regard. In summary, the paper’s contribution lies in the introduction of an innovative voltage level shifter design capable of addressing the voltage signal conversion demands in a manner that efficiently reduces propagation latency. The approach’s foundation in the standard current mirror topology, supplemented by novel components, marks a notable departure from traditional designs. The empirical evaluation showcases its superiority in terms of propagation delay improvement and robustness in corner analysis compared to contemporaneous methodologies.