A Low Power and Low Noise, Self Body Biased Low Noise Amplifier

In this article, a low-power, low-noise, self-forward-body-biased LNA is proposed. The proposed LNA uses inverter-based, body-biased gm-boosting techniques. In order to lower the threshold voltage for low power consumption, two resistors are employed for body bias, negating the requirement for external bias. Without utilizing additional DC current, an inverter-based architecture is used to enhance gm such that it combines the gm of NMOS and PMOS. A source degeneration inductor along with a T-network at the input is used for input matching. The proposed LNA is designed by using TSMC 65LP CMOS technology. The post-layout simulation of the proposed LNA achieved a peak gain of 24 dB, a noise figure (NF) of 1.1 dB, and a third-order intercept point (IIP3) of -16 dBm with a power consumption of 154 uW.