Multi-port Register File Implementation Using SDP Approach for Optimized Area and Power

In recent years, demand for multi-tasking with sustained high-performance is increasing in mobile CPUs. This puts focus on achieving high throughput, which can be done by using lot of multi-port memories, since they can process many operations per clock cycle. In this paper, we present one such memory config, a 128×32-bit register file supporting 10-write and 20-read operations (10W/20R). This is implemented using Structured Datapath Placement (SDP) approach in 3nm technology node supporting >3GHz High-Performance (HP) core. Improvement around 54% in power and 42% in area is demonstrated using this approach over conventional Tool Synthesis, Place and Route (PnR) flow. Various logic and implementation techniques which helped in getting above gains are discussed.