DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications

Functional verification problems such as clock domain crossing (CDC), reset domain crossing (RDC), X-propagation and design for testability (DFT) readiness have been the mainstay of hardware verification flow for some time now. With the ever-increasing chip complexity for modern-day mobile, multicore systems-on-chip (SoCs) with built-in advanced image processing, and scalable AI microcontrollers with billions of gates and numerous clock domains with ultralow device geometries, these problems are not only more significant nowadays, but need to be addressed very early in the design process for a timely tape out and first-pass Silicon success; failing which, there will be prohibitively expensive design bug fixes and costly design iterations. Static methods that perform search and analysis techniques to check for failures under all possible test modes, scenarios, and cases, have emerged as a very promising paradigm for solving these problems early, during RTL design. This paper describes a novel static verification, debug, and sign-off tool, Meridian DFT, that can detect specific design issues affecting testability at early RTL in presence of one or more test modes and provide ways to debug and quantify such issues. We present results on large scale (100+ million gates) industrial designs from mobile SoC and AI/Edge domain chips.