Enhancing Efficiency and Effectiveness: An Innovative Design for Multipliers on FPGA

Multiplication is an essential arithmetic operation that is employed in many domains, including image processing and machine learning. Despite high-performance FPGA multiplier availability, restrictions exist - limited DSP blocks and locations reduce efficiency for smaller bit widths. This work emphasizes the need for better custom soft multiplier FPGA designs targeting improved speed and lower resource usage. This paper introduces innovative architectures for multipliers on FPGA, aiming to enhance performance and resource efficiency. Our proposed designs leverage FPGA features such as lookup tables [LUTs] and fast-carry chains. In comparison to existing solutions, the proposed accurate multiplier achieves a significant reduction in lookup table utilization, while the proposed approximate multiplier demonstrates improved efficiency in critical path delay [CPD]. Area, latency, and PDP performance metrics are being taken into consideration. The detailed analysis is carried out for 16x16 proposed multipliers in Vivado.