Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework

In the present era of the global design supply chain, several untrustworthy entities can be involved. From an intellectual property (IP) vendor’s perspective, an attacker in the system-on-chip (SoC) integration house may pirate the design IP and/or claim ownership. This paper introduces a novel watermarking methodology using design parameter driven encrypted dispersion matrix with an eigen decomposition-based security framework as a detective countermeasure against the aforementioned threat. Our work considers the IP vendor as the defender and the SoC integration house as the attacker. The proposed approach presents a security framework that extracts the characteristics of the IP vendor selected design space parameters and the design space’s characteristics in terms of IP vendor chosen resource configurations and exploits them as unique features to embed them as digital evidence for protecting IP design. In the presented approach, secret security constraints are extracted for embedding into the IP design using a number of components such as dispersion matrix generation block, eigen decomposition block, AES encryption block, and high level synthesis (HLS) register allocation block. The results of the proposed approach, in comparison with prior works, offer an improvement in the probability of coincidence upto ~107, tamper tolerance upto ~10231, and entropy upto ~10545 at negligible design overhead.