A Novel Graphical Technique for Multiple Harmonic Mitigation in a Two-Level Inverter with Only Two Switching Angles

This paper introduces a novel graphical technique for selective harmonic mitigation (SHM), substantiated by experimental data. This approach identifies maximum modulation indices for different harmonics while adhering to a constraint of two switchings per quarter cycle. The study demonstrates the effectiveness of the technique in mitigating harmonics within this range and optimizes harmonic suppression using variable DC voltages. The research uncovers multiple solution regions, addresses concerns at higher harmonics, and reveals an infinite solution space for selective harmonic mitigation. In particular, the approach achieves a 10% SHM bandwidth under a 5% IEEE 519-2022 standard limit and defines operating zones for enhanced management. The study also covers individual and cluster harmonic mitigation, highlighting the versatile application. The proposed graphical technique solves nonlinear SHM equations with inequalities and provides all possible solutions at every modulation index for single or multiple harmonic mitigations. The proposed technique is experimentally verified using an FPGA-based hardware prototype developed in the laboratory, and the results are presented. It is shown that up to seven harmonics can be simultaneously mitigated at certain modulation indices with only two switchings per quarter.