MSDF-SVM: Advantage of Most Significant Digit First Arithmetic for SVM Realization

The implementation of Support Vector Machine (SVM) for processing high-dimensional datasets and achieving both accuracy and fast response times poses substantial challenges, especially with the growing size of modern datasets and feature dimensions. To address these challenges, this paper introduces MSDF-SVM, a novel approach that exploits the parallelism and digit-level pipelining capabilities of FPGA devices and leverages online arithmetic. The proposed method takes advantage of an efficient dot-product unit for computing distances to support vectors and then detects their signs. This process is done on incoming data samples in a serial manner, which reduces the area and memory requirements for each classifier instance. This allows for the optimal utilization of parallel instances based on the target FPGA devices. MSDF-SVM dynamically terminates unnecessary computations, which occurred over 65.6% on average, resulting in a considerable energy reduction. Notably, this work represents the first effective utilization of online arithmetic to design an SVM accelerator. Experimental evaluations on real-world applications, including voice gender detection and emotion classification, demonstrate the remarkable performance improvements and reduced energy consumption achieved by MSDF-SVM compared to previous designs.