Signed-Digit Addition Based on CNFETs and Ternary Logic

This paper presents three novel designs for a signed-digit half adder based on ternary logic implemented with carbon nanotube FETs (CNFETs). In the past, multiple-valued logic (MVL) has mostly been associated with some form of multi-threshold CMOS and, in certain cases, by relying on depletion-mode MOSFETs which are largely absent from current processes. However, CNFETs, which have emerged as a promising avenue for VLSI evolution beyond CMOS, offer an appealing alternative for MVL since it is possible to adjust their threshold which is inversely proportional to the nanotube diameter. For this reason, they have received considerable research attention as an enabling technology for ternary logic and other forms of MVL. Here, we use ternary logic to represent redundant binary digits. The three proposed designs adopt three different approaches which together form a cohesive framework for ternary logic design in general. For the first two designs, the operands first pass through a ternary decoder so that the subsequent core logic can be designed with ordinary binary gates, with the results then passing through ternary encoders to return to the ternary domain. The difference between the two is the binary encoding used for the core logic. In the first design, a one-of-three (one-hot) encoding is used, such that 3 lines are required per operand. In the second design, a binary encoding on 2 lines is employed. A third design is proposed which avoids the binary core and works directly with the ternary signals. All three designs achieve significant savings in number of transistors compared to similar reported efforts. All designs are fully active and avoid both resistive loads and transmission gates. Design principles are emphasized.