Reducing Power Dissipation in Adiabatic ECRL Inverter Based on All-NMOS Transistors

The world of microelectronics has been revolutionized by technology, and the Integrated Circuit (IC) has been the primary driving force behind all these advancements. Over time, improvements have been made to ICs to enhance their performance, like increasing clock frequency or increasing the number of transistors, but with this advancement comes with the drawback of more power dissipation in our IC, which has been combated in several ways one of which is the use of adiabatic logic circuit. This research studies how power dissipation is reduced when the rise and fall time of a power clock pulse (Vdd) is reduced in an ECRL inverter circuit and proposes a modified circuit that dissipates lesser heat at the same rise and fall pulse signal.