A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures

Computation-in-memory (CIM) is a promising solution to tackle the memory wall problem in big data and artificial intelligence applications. One possible approach to implement such a scheme is to use nonvolatile resistive memory technologies like spin transfer torque magnetic RAM (STT-MRAM) or resistive RAM (ReRAM). However, despite all the attractive features these technologies offer, they introduce new types of defects different from conventional SRAM technologies. Therefore, there is a need for dedicated testing algorithms that can detect such defects. In this paper, we proposed a testing scheme for CIM-capable memories that utilizes trim circuitry to dynamically switch between standard memory testing and CIM testing modes based on the speed and accuracy requirements, eliminating unnecessary testing overheads. This feature provides significant test time reduction while preserving the quality of the test. The proposed method is compatible with existing memory built-in self-test (MBIST) architecture and can be used for different types of emerging resistive memory technologies.