Microarchitecturally Exploring Fault-Tolerance and Timing on Silicon on Chip

This paper presents a micro architectural exploration of fault-tolerance and timing behavior on silicon on chip. Silicon on chip represents a full-size mission in designing reliable hardware with excessive timing accuracy because of its demanding situations resulting from layout variability, disorder densities, clock jitter, and different assets of noise. To improve the reliability of those devices, this work investigates the effect of redundant hardware systems, dynamic voltage and frequency scaling, and gentle-blunders mitigation strategies. The reliability and accuracy of the proposed systems were evaluated in two fundamental kinds of subthreshold versions: random device versions and systematic tool variations because of overlaying and doping defect styles. Effects illustrate that the redundancies and voltage scaling strategies can increase the robustness of the gadget against subthreshold variations, providing processors with better accuracy and reliability.