High Performance VLSI architecture for Sense Amplifier based Flip flop

High-speed, low-power operation is appropriate, a sense-amplifier-based flip-flop (SAFF) is suggested in this study. Utilizing the new sense-amplifier stage and single-ended latch stage, the flip-power flop’s and latency are greatly decreased. The latch has limited-cutoff design to ensure flawless and conflict-free operation. The suggested SAFF can also operate at low voltage thanks to the use of MTCMOS optimization. In comparison to the standard SAFF, the suggested SAFF reduces the CK-to-Q delay by 41.3%, the consumption of energy by 36.99% (at a rate of 25% input data toggling). According to post-layout miniature findings based MTCMOS on a SMIC 55nm. Additionally, compared to the flip-flop called master-slave, the energy and lag are lower (MSFF). The SAFF’s that are suggested, the power-delay product improves by 2.7% and 3.5%, respectively, over the traditional SAFF and MSFF. The proposed flip-flop has an area of 8.12m
²
(or 5.8 m by 1.4 m), which is comparable to the traditional SAFF. With the suggested SAFF, reliable operation might be achieved at low supply voltages like 0.4V with the use of optimization.