Network on Chip(NoC) Mesh Topology FPGA Verification: Real Time Operating System Emulation Framework

Network on Chip (NoC) is an upcoming paradigm that copes with the increasing complexity and communication requirement of future System on Chip (SoC). In this paper, we have modeled the NoC traffic characteristics under queuing theory, demonstrating clustered phase over synthetic traffic specially under varying packets and queue/buffer size.We have also demonstrated IP core design cycle verification scalable framework in a SoC design paradigm, over a 3x2 mesh NoC framework on Intel Field Programmable Gate Array Logic (FPGA) Cyclone-II FPGA (EP2C70F896), 95nm Very large Scale Integration (VLSI) technology chipset for functional and cycle behaviour characteristics through State-of-the-art software Quartus Prime Computer Aided Design(CAD) system. The task management and synchronization of the traffic generation and reception is performed with the help of real-time operating system (RTOS) so as to demonstrate the Device Under Test (DUT). Such frameworks can helps in generating scalable NoCs and their cycle behaviours in re-configurable environments and applications. .