Desynchronization of a Synchronous Circuit to Synthesize Self-Timed Circuit

Within the article the issue of automatic synthesis of self-timed circuits from the original synchronous description in the Verilog language is covered. The key stage in the synthesis of a self-timed circuit is the procedure that identifies the circuit pipeline organization followed by desynchronization. The essence of desynchronization is to replace the global clock signal with a set of request-response interaction signals between functional blocks within an interstage pipeline. This method uses the open source Yosys synthesis toolkit to transform the original behavioral description into a set of logical equations and library elements. The resulting set is subjected to a desynchronization procedure and is formed as a task for further synthesis of a self-timed circuit in the Verilog language. In this case, indication of the end of transient processes is implemented both in combinational and memory circuits.