FPGA Implementation of Reconfigurable Address Generator for Various Standard Interleaver in Xilinx FPGA

This work presents new and practical methods for constructing multi-standard adaptive architectures for address generators and interleavers. The main objective is to reuse hardware resources whenever feasible and maximize hardware resources for support of multiple standards. The study provides a reasonably cost reconfigurable architecture for address generation and interleaving that meets with WLAN (802.11a/b/g and 802.11n), WiMAX (802.16e), and 3GPP LTE requirements. In order to reduce hardware cost and implementation complexity, the study recommends a straightforward algorithm and a reconfigurable architecture that do away with costly computations like the floor function for WLAN/WiMAX and both the mod and floor functions for LTE.