Efficiency Evaluation of Scalable Multiply and Accumulate Architectures in DSP: A Comparative Study of LUT Based and LUT-Less Based Approaches

Multiply and Accumulate (MAC) units are widely used in digital signal processing. They are crucial for activities like correlation, convolution, and filtering, which allow for fast and effective signal processing. A fundamental component in modern digital signal processing systems, these scalable units serve as the foundation for a wide variety of DSP algorithms. The distributed arithmetic method, which offers reduced computational complexity while preserving accuracy through parallelism and distributed multiplication operations, is a highly effective way for creating Multiply and Accumulate (MAC) structures in digital signal processing. A scalable Multiply and Accumulate (MAC) architectures are shown in this article. Also, explored the design of multiply and accumulate structures at various bit-widths: 4, 8, 16, 32 and 64-bit versions, as well as analyzed LUT-based and LUT-less approaches. Significant variations in space and power consumption between LUT-based and LUT-less systems are highlighted by the data in the article for a variety of bit-width configurations. A quantitative examination shows that whereas LUT-less devices continue to have a smaller footprint and lower power consumption even on larger bit-widths, LUT-based solutions clearly consume large area and consumes more power as width of the bits expands. The proposed method is designed and simulated using Xilinx Vivado 2022.2 software.