Low Power and Area-Efficient Hybrid Adder for ALU Operation

This study describes a new low-power, area-efficient hybrid adder architecture for arithmetic logic unit (ALU) operations in digital systems. The goal is to integrate multiple adder architectures to reduce power consumption while increasing speed. The proposed hybrid adder combines pass transistor logic (PTL), gate diffusion input (GDI) logic, and modified GDI (MGDI) logic to provide carry and sum outputs, that reduces power consumption and improve circuit performance, with less number of transistor count. Cadence Virtuoso is used for evaluation using a 45 nm generic process design kit (GPDK) and the power supply voltage is set at 1.2 V. A comparative analysis with the existing adders has been performed considering parameters like propagation delay (PD), average power (AP), and power delay product (PDP). By balancing power consumption, circuit performance, and space utilization, the research adds to adder design. Designers and researchers of efficient adders in portable and battery-powered devices will find this information useful.