DSCAM+: Latency-Guaranteed FPGA-Based Content Addressable Memory for SDN-Enabled Forwarding Plane

This paper presents a new approach for implementing high-capacity content-addressable memories on field programmable gate arrays (FPGAs). This approach introduces a novel configurable hardware architecture complemented by a multi-objective heuristic optimization algorithm. This algorithm explores the design space and identifies the near-optimal configuration parameter values for a given search table content. In this approach, the matching operation is carried out partially using synthesized circuits within the FPGA logic fabric and partly relies on an SRAM-based bitmapping technique. The balance between logic and memory resource utilization can be adjusted to accommodate constraints and design priorities. The approach supports large search tables, offers high throughput and short-latency searches, and can be reconfigured to adapt to new matching rules. This adaptability makes it particularly well-suited for IP address lookup in SDN-enabled data planes. Experimental results demonstrate the effectiveness of this method. It enables the implementation of an IPv4 forwarding table with more than 520,000 prefixes on a cost-effective AMD-Xilinx UltraScale+ FPGA. This implementation delivers a lookup latency of under 26 ns and a throughput of over 235 million lookups per second. The source code for this work is accessible on GitHub.