FPGA Design of a Reconfigurable UART IP Core and its SoC Implementation for IoT Applications

Data interruption during serial transmission is a commonly encountered issue. It is mostly caused by inappropriate buffer size allocation between the two Universal Asynchronous Receiver Transmitter (UART) modules to store the entire data chunk being sent or received. This problem can be mitigated if both modules can communicate with each other to adjust the size of their Transmit (Tx) and Receive (Rx) buffers through either static or dynamic reconfiguration. In our proposed design, both these approaches have been used to modify the typical UART architecture. In the ‘Instantiation’ mode, the sizes of Tx and Rx buffers are specified statically when the core is instantiated in a project during simulation and synthesis steps. In the ‘Runtime’ mode, the buffer sizes are dynamically adjusted based on the communication between the CPUs at the two ends. In the later case, the Tx UART modifies its own buffer size and then sends control packets to configure the size of the Rx UART preceding the data transfer. A System-on-Chip (SoC) based on RISC-V SwerRV IP Core and the modified 16550 UART IP Core has been developed, tested, and synthesized for both Artix-7 FPGA and TSMC 180nm ASIC technologies. The design demonstrated correct UART behavior while adding configurable data buffers at both ends to provide non-blocking data transfers up to a buffer size of 32KB.