Design and Analysis of Full Adder and Full Subtractor Circuit Using Hybrid Logic Style

Minimization delay and low-power consumable logic devices are the significant challenges in designing a digital microelectronic circuit. Most electronic gadgets comprise arithmetic logic units (ALU), a significant part of the processor. The processors are consuming high power and causing more delay due to the low performance of arithmetic logic units. The performance of the electronic circuit is enhanced by increasing the performance of the ALU. The essential component of an ALU is an adder circuit. The adder circuit is used for addition and other arithmetic operations such as multiplication, division, and address calculation. In this article, the design and analysis of full adder and full subtractor circuits are carried out. It is designed using the XOR-XNOR logic circuit, which consumes less power and minimizes delay. The performance of these circuits is dependent on the XOR-XNOR logic module. The difference and borrow circuits are designed using CMOS logic and transmission gate logic. An XOR-XNOR circuit can reduce delay and power and get full swing (FS) output. The hybrid logic style based full adder and subtractor parameters like power, delay, noise margin, and the number of transistors.