Design and Evaluation of Arithmetic and Logic Unit Using Simulated Annealing

Metaheuristics are widely used in finding various design alternatives and overcome the limitation of traditional approaches for circuit design. Arithmetic and logic unit (ALU) is an important part of processing unit capable of performing various arithmetic and logical operations. Population based simulated annealing is used for design of ALU in proposed work. Two benchmark ALUs from LGSynth'91 is realized using proposed work. Proposed work saved the gate count by maximum of 51.83% and transistor count by 92.03% over baseline ALUs reported in literature. To validate the flexibility in choosing the resource type and objective function supported by proposed work, functional units of proposed ALUs are designed using three resource types (2-input logic gates, 2:1 MUX, Reed Muller) and three objective functions (resource, transistor and level count optimization). A graphical user interface is developed for generation of Verilog scripts and test bench for verification of functional blocks. Proposed ALUs are synthesized on FPGA and Cadence Genus-90nm standard cell library to compare with conventional designs. MUX based ALU design used almost same number of lookup-tables and consumed same power as conventional designs with an advantage of single resource type for design of ALU confirming their suitability for FPGA implementation. ALU designed using logic gates saved area by 3.39% and critical path delay by 9.37% over conventional designs and making it suitable for ASIC implementation.