A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator

This paper presents the method to obtain an optimized set of power loading coefficients (PLC) considering the transmitter's power- and area-efficiency for discrete multitone (DMT) modulation wireline transceivers (TRX). A simple way to estimate the PLCs is to invert the channel loss profile; however, to achieve an optimal signal-to-noise ratio (SNR), the PLCs should be multiplied by an additional value calculated by the peak-to-average power ratio (PAPR) of the TX output signal. In this work, we show how to calculate this value using the PAPR. Also, the TX DSP datapath where the PLCs are applied has an optimal bit-width in terms of the area given the bit-error-rate (BER) target, but the register-transfer-level (RTL)-based BER simulation iterating with various bit-widths of the DSP's internal datapath is significantly time-consuming. To address this, we designed a fixed-point DMT TRX simulator in MATLAB that allows us a fast iteration-based performance-area optimization of the DSP. With the design parameters including the PLCs obtained by the developed fixed-point simulator, the BER of the DMT TRX achieves 1.8E-5 with only 4-bit PLCs to communicate over a channel exhibiting 10 dB insertion loss at Nyquist without considering the analog front-end.