Model Based Design of FMCW Radar Processing Systems on FPGA Platforms

The use of high level synthesis (HLS) tools is progressing in the industrial and academic worlds as they have gained in maturity. In the last few years, they are commonly applied to design hardware accelerators for ASIC and FPGA targets. Indeed, they enable signal processing algorithm integration in a shorter amount of time than methodologies based on handmade RTL design. Moreover, suitable behavioral description facilitate design space exploration to fulfil system constraints while minimizing other parameters. In this article, HLS tool abilities to design complete signal processing systems are evaluated. To this end, a commonly used FMCW radar signal processing system is deployed. The article presents demonstrate that a large set of trade-off solutions can be produced thanks to the described models. In a second time, the interest of the proposed approach is compared to optimized multicore SIMD implementations that are also relevant to give flexibility to FMCW radar embedded systems.