Image Processing Algorithm Design for Low-Light EBCMOS Devices Based on FPGA

In this study, a hardware platform based on the Xilinx 7-series Field-Programmable Gate Array (FPGA) is employed. The design of a Static Storage Control Module and a Median Filtering Module is accomplished through programming in the Verilog hardware description language using Vivado software. The functionality of these modules is rigorously verified through logical validation using Modelsim software. The algorithm is applied to process low-light images captured by a custom EBCMOS image sensor. Comparative analysis with software testing platforms reveals a substantial improvement in image processing speed when utilizing the FPGA-based hardware resources. This improvement allows the processing of 1 pixel per clock cycle. As a result, this work lays the foundation for the design of lightweight, integrated data acquisition systems for the nextgeneration night vision helmet systems.