A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA

Maximum likelihood (ML) estimation algorithm is a special case of Bayesian estimation method in the field of direction of arrival (DOA) estimation. The ML algorithm exhibits robust capabilities with small estimation errors, making it applicable to challenging conditions, such as dealing with correlated signals and limited snapshots. However, a drawback of the ML algorithm is its multidimensional iterative nature, which results in huge computation and time consumption. To address these challenges, this article proposes a hardware implementation of the ML algorithm on a field-programmable gate array (FPGA). The design scheme presented in this article uses alternating projection (AP) to transform multidimensional operations into 1-D operations, effectively reducing the computational load. On the other hand, combined with hardware characteristics, pipeline design is used to save computing time. This design achieves a time reduction of approximately 60% in contrast to the design without the pipeline. In addition, when the number of sources is 1, the number of snapshots is 1000, the signal-to-noise ratio (SNR) is 10 dB, and the number of elements is 10, the root mean square error (RMSE) can be close to 0.02°. This exemplary performance serves as evidence that the hardware implementation in this article ensures accuracy.