Characterizing CNTFET Logic Gate and Adder Performance Trade-offs by considering CNT Tube Diameter and Dielectric Constant

CNTFETs are emerging as a possible replacement for conventional silicon-based transistors due to their unique properties, which include increased electron mobility, high power density, high switching speed, increased transconductance, and superior electrostatic control. We examine the efficacy of CNTFET fundamental gates by varying parameters such as tube diameter (Dent) and material dielectric properties (s). In order to conduct these simulations, we have integrated the Standford CNTFET model library into CADENCE (Virtuoso). This paper investigates the influence of tube diameter and dielectric constant of CNT (32nm technology) on the performance of CNTFET -based digital circuits. Which exhibits the new design of CNTFET internal properties for optimizing the performance of digital circuits in terms of delay, power consumption, PDP, and EDP. By increasing the CNTFET tube diameter from 1.0179 nm to 1.9575 nm while maintaining a dielectric constant of 3.9 (silicon dioxide), the delay will be reduced by 38.63% for an INVERTER, 42.22% for an AND gate, 57.04% for an OR gate, 49.01 % for a Half-adder, and 36.97% for a Full adder. Choosing the tube diameter and dielectric constant of a CNTFET is the most crucial parameter for optimizing the performance of CNTFET -based digital circuits. In the future, the effectiveness of CNTFETs based on 16-nm technology in digital circuits with varying oxide thickness, pitch, and tube positions can be evaluated.