Improvement and Realization of CAM-based Ethernet Circuits

Content-addressable memory is widely used in the core circuit of the network switch. For the increasing amount of forwarding data in the network requirements, this paper will be a typical serial design circuit module to improve the parallel design, in the case of reducing the use of hardware resources overhead, both to ensure that the circuit to achieve high-speed data lookup matching, storage address updating and synchronization of the time aging, and at the same time to reduce the data exchange when the data exchange to produce the conflict probability when exchanging data, improve the overall circuit efficiency, and achieve the performance optimization of the switching circuits. In this paper, the Ethernet switching circuit designed with improved content-addressable memory is simulated on the Xilinx Virtex-7based Field Programmable Gate Array (FPGA) development platform, and the simulated waveforms of the improved circuit and the expenditure of hardware resources are given to verify the validity of the scheme and the correctness of the theoretical analysis. and the correctness of the theoretical analysis.