Performance Analysis of Ternary NAND Gate Based on FinFET Models

The rising complexity of digital circuits based on binary logic demands the use of multivalue logic. This article outlines the detailed device level behavior of LVT FinFET model and a ternary NAND gate is designed and compared using three distinct FinFET models: LVT, SVT, and HVT. The simulation results show the power consumption as 10.7, 7.5 and
$5.01\ \mu\mathrm{W}$
for LVT, SVT and HVT models, respectively. Further, the obtained power delay product (x 10
⁻¹⁵
J) is 379.26, 265.52 and 175.65 for LVT, SVT and HVT models, respectively. The anticipated ternary NAND gate design is convenient for optical computing, error detection and cryptographic algorithms.