A High-Speed Sense Amplifier Based Flip Flop with a Single Ended Latch Design and Low Voltage Operating Capabilities

This paper presents a sense amplifier-based flip flop (SAFF) with low power and high-speed operation capabilities. The power consumption and delay of FF improved after using the single-ended latch design. Contention and glitch-free operation are achieved through conditional cutoff. The study also shows a comparison of the modified SAFF with all previous flip-flops. The PDP of the modified SAFF improved to 60.7% compared to Jeong's SAFF, and the CK-Q delay improved to 44.6% compared to the MSFF. The modified SAFF provides operation even at very low voltages of 0.45 volts. The schematics of all SAFF are simulated using gdpk90nm technology in the Cadence Virtuoso tool.