Analysis of a 10T Full Adder with a new 4T X-NOR using FD-SOI 22nm Mix-VT Technology

Massive technological advancements are done on VLSI regarding propagation delay, performance analysis, and reducing channel length. As a result, electronic devices are becoming more portable nowadays. One of the significant concerns of VLSI is reducing the leakage current as the channel length is getting shorter day by day. As a result, the control of the gate of MOSFET over the channel length is weakening. So, a lot of leakage current passes over the entire MOSFET. To solve this problem, a new type of geometrical change is introduced in MOSFET. This innovation is known as Fully Depleted Silicon on Insulator (FD-SOI). Also, pass transistor logic is being used instead of conventional CMOS logic to reduce the chip device size. This paper focuses on reducing the no. of transistors and minimizing the power consumption simultaneously. In this manuscript a comprehensive analysis was done on Cadence Virtuoso 22nm FD-SOI technology where the proposed XNOR takes only 26% and proposed Full-Adder takes only 25% of the power consumption than conventional CMOS in different power supply.