Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic

In today's fast-paced technological era, electronic devices must be both speedy and energy-efficient to keep up with rapid advancements. Developing energy-efficient digital devices for real-time applications is critical in VLSI research. The adiabatic process of logic circuits is used to develop an adder with high performance and ultra-low power dissipation. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) have been explored with the scaling of devices. The proposed circuit contains a new type of adiabatic circuit that works excellently for low-power dissipation. A comparison is made with the conventional CMOS adders, such as half and full adders and newly developed adiabatic logic circuits. All the experimental simulations have been carried out using LTSpice software for 16nm and 22nm LP PTM models by changing frequencies from 0MHz to 25MHz, taking rise and fall time as 1n & 2n seconds respectively. We have also varied the load capacitance from 0f to 10f. The outcomes obtained from the experiment indicate the effectiveness and capability of the newly proposed circuit, which is 40% less power consumption and 22% less energy consumption for both 16nm and 22nm, respectively, using 0f as load capacitance.