XOR-Free Approach Towards Realization of Low Pass FIR Filter in Bio-Medical Signal Acquisition : Vedic Multiplier-based ASIC Implementation

FIR filters implementations using digital adders and multipliers frequently use power-hungry XOR gate-based combinational logic circuits. Through this paper, we propose a novel strategy to eliminate the XOR gates from the FIR filter architecture. The architecture is implemented using modular Urdhva Triyakbhyam sutra Vedic Multiplier, in which the multiplier output bits are computed by careful examination and mapping of multiplicand and multiplier bits without any 1-bit adders. We also propose an XOR-free implementation of 1-bit Full Adder (FA) used for designing higher wordlength adders required for the realization of the FIR filter. The aforementioned multiplier is used for the ASIC design of low-pass FIR filter for de-noising during signal conditioning in biomedical signal acquisition systems. ASIC design has been carried out for the SCL 180 nm CMOS technology node using the various tools of Cadence Digital Design and Signoff suite. ASIC implementations reveal an 11.85% reduction in on-chip area and a 20.82% reduction in power consumption compared to the state-of-the-art FIR filter architectures reported in the literature.