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Low-Additive Phase Noise Low-Power Static Frequency Dividers | IEEE Conference Publication | IEEE Xplore

Low-Additive Phase Noise Low-Power Static Frequency Dividers


Abstract:

This paper demonstrates two different static frequency dividers in InP 250nm with low additive phase noise performance while keeping the DC power consumption below 190 mW...Show More

Abstract:

This paper demonstrates two different static frequency dividers in InP 250nm with low additive phase noise performance while keeping the DC power consumption below 190 mW. The core dividers circuit consists of current-mode logic latches in leader-follower configuration, and the frequency range of operation is measured up to 32 GHz. The static divide-by-two and synchronous divide-by-four achieve −138.2 dBc/Hz and −143.5 dBc/Hz additive phase noise at 10 kHz offset from 10 GHz input frequency while consuming 137 mW and 189 mW, respectively. The corresponding self-oscillation frequency (SOF) of divide-by-two and synchronous divide-by-four dividers are 7.8 GHz and 3.9 GHz, respectively. The synchronous divide-by-four is able to generate more than −13 dBm output power over a wide range of frequencies. The low power consumption and low phase noise operation are achieved by employing resistive load, reducing the size of the transistors, and optimizing the circuit layout to reduce parasitic capacitance.
Date of Conference: 21-24 January 2024
Date Added to IEEE Xplore: 21 February 2024
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Conference Location: San Antonio, TX, USA

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