A 3.6GHz Highly Efficient Dual-Driver Doherty Power Amplifier

This paper presents an advanced Doherty-type power amplifier architecture, which uses two driver amplifiers embedded in the Main and Peaking paths of the Doherty stage. Due to the biasing configuration, the power consumption of the Driver stage is reduced in the back-off, enhancing the backoff efficiency, while improving the load modulation and the power utilization factor of the transistor devices of the power amplification stage. Some of the design trade-offs introduced by the Dual-Driver Doherty are discussed and investigated using a simplified transistor model. Finally, a demonstrator is designed using GaN-HEMT devices for all amplifiers and evaluated to investigate the performance of the line-up with modulated signals. The measured performance after digital pre-distortion using a 100MHz wideband signal centered at 3.6GHz, showed at an average output power of 40dBm a modulated line-up efficiency of 48% and an ACLR of -45dBc with average gain of 25.7dB.