Investigating Mesa Structure Impact on C-V Measurements

Capacitance-voltage (C-V) measurements play a crucial role in evaluating semiconductor device performance by revealing vital parameters such as doping levels and charge carrier behavior. This study specifically investigates the impact of mesa structures on C-V measurements in 4H-SiC PiN vertical diodes. Our analysis uncovers distinct capacitance values per unit area among diodes with varying diameters within the same diode family. These findings underscore the limitations of conventional capacitance equations formulated for planar devices when extended to mesa-structured devices. To separate the capacitance portion dependent solely on the PN junction’s area from the overall depletion capacitance, which is influenced by the device’s geometry, we applied a methodology involving multiple C-V measurements across diodes with differing diameters and validated the experimental outcomes through rigorous calculations. This enables the utilization of standard capacitance equations. Neglecting the impact of device geometry has the potential to introduce significant inaccuracies in critical device parameters. The proposed methodology addresses these limitations, offering valuable insights to enhance the accuracy of extracted quantities from C-V measurements. Furthermore, it provides guidance for interpreting experimental data obtained from devices incorporating mesa structures.