Network on Chip for 2D Mesh Toplological Structure in HDL Enviornment

Network on Chip (NoC) refers to the network variant of the multiprocessor system on chip (MPSoC). The RoC approach has been demonstrated to be one of the most effective methods for the efficient utilisation of interconnections, and it facilitates the exchange of data between multiple nodes integrated on a single processor. The topology, switching, and routing techniques are crucial to the design of the NoC architecture. The paper concentrates on the design of a 2D NoC router and its application in configuring a (4×4) mesh topological NoC. To resolve the RoC's nodes, the XY routing technique is implemented. It is one of the simplest methods for designating nodes and routing data packets from one node or processing element to another within a NoC. The NoC layout is created using the VHDL programming language and is simulated using Xilinx 14.2 and simulation software. The design is validated on a Virtex-5 FPGA with 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit data transfer between nodes when the NoC is fully connected and operational. In addition to analysing the hardware parameters and detailed report of the developed NoC Chip, the FPGA synthesis parameters are also analysed.