Simulink Modeling and Performance Verification of 2.4-GHz Fractional-N Reference Oversampling PLL with 20-MHz Loop Bandwidth

In this paper, we propose a Simulink model for a mixed-signed 2.4 GHz fractional-N reference Oversampling Phase-Locked Loop (OSPLL) to meet the requirements of modern wireless communication equipment that require low noise specific frequency clocks. The proposed OSPLL uses Bang-Bang Phase Detectors (BBPD) with an Oversampling Rate (OSR) to improve the equivalent reference frequency, and a Digital-To-Time Converter (DTC) to reduce the impact of high-frequency shaped noise in fractional-N mode. We verify the proposed OSPLL using MATLAB Simulink, and it achieves a Root-Mean-Square (rms) jitter of 303 fs in fractional-N mode with a loop bandwidth of 20 MHz when the reference frequency is 60 MHz and OSR is 40.