Design and Implementation of an Improved Watchdog Timer for Memory Applications

A watchdog timer is a type of electrical timer that detects and recovers from computer errors. In embedded systems and other computer-controlled equipment where individuals are unable to immediately access the equipment or react to faults in a timely way, watchdog timers are often employed. Limiting the amount of CPU time accessible to untrusted programmes in a sandbox can assist avoid denial-of-service attacks. The computer automatically refreshes the watchdog timer during normal operation avoid the timeout. The timeout signal is used to stop a programme from running indicate whether or not a corrective action should be taken. The architecture and design of an improved adjustable windowed watchdog timer for memory applications are described. The watchdog has several defect detection algorithms built in, this makes it more durable. In terms of capabilities and operations, it may be used to monitor any real-time processor-based system. architecture may be modified to a variety of situations may be readily tailored to different applications while keeping the overall system cost low, and owing to the processor reliance the recommended watchdog has less time limitations than the present watchdog. The simulation results are used to investigate the effectiveness of the proposed watchdog timer in detecting and responding to errors. Verilog is used to code the design. Xilinx Vivado 20.1 was used to implement the design. By injecting flaws into the programme while the processor is running, the design is evaluated in real-time hardware.