Optimization of Leakage Power Dissipation in CMOS Inverter using Self biased and W/L Scaling Techniques

Now a day's due to the rapid development of nanoscale device, low power dissipation has grown to be a serious problem for researchers and VLSI designers. We are presenting the novel low power schematic of a CMOS inverter. the archi-tecture of hybrid (V
SB
) and stacking techniques is proposed to minimize the overall leakage power. Cadence Virtuoso Simulation tools has been used for analysis. The analysis of conventional approach, substrate biased approach, and the combination of (V
SB
) and stack approach for reducing leakage current and overall power consuption in CMOS inverter. In comparison with the conventional strategy and the stack approach, the power dissipation of the combined (V
SB
) biased and stack approach improve the performance of CMOS inverter at the least cost of area in 45nm cadence virtuoso tool.