Design and Analysis of FinFET Based Ternary Multiplexer

Multivalue logics have emerged as a considerable advancement in the field of digital electronics, providing solutions to the limitations imposed by binary logic. Ternary logic is considered an innovative tactic within the field of multivalue logic. In this article, an energy efficient ternary multiplexer is designed using standard voltage threshold (SVT) 18nm FinFET model in Virtuoso tool provided by Cadence and its performance is compared with the existing CMOS design. The simulation results obtained shows power consumption as 39.76 μW, transient delay as 0.34ns and power delay product as 13.51 (x 10
^-15
J) for FinFET based design. The designed ternary multiplexer architecture is beneficial for applications where high speed signal routing is required.