Design and Analysis of FinFET Models Based Ternary NOR Gate

There is a growing demand for multivalue logic due to the rising complexity of digital circuits based on binary logic. This article presents an in-depth review of the device level characteristics pertaining to the HVT FinFET model. The ternary NOR gate design and performance comparison are carried out using the LVT, SVT, and HVT FinFET models. Based on the results, the power consumption values for the LVT, SVT, and HVT models are recorded as 6.1, 3.6, and 2.4 (μW), respectively. Furthermore, in the case of LVT, SVT, and HVT versions, the power delay product (x 10
⁻¹⁵
J) is measured to be 62.14, 36.86, and 24.04, respectively. The suggested architecture of ternary NOR gate has advantages in several domains such as data compression, quantum computing, and signal processing applications.