Design of Encoder based Half-Adder using GNRFET Technology in Ternary Logic

The ternary logic technology is best alternative over the traditional binary logic. Because of it provides the simple and power efficiency in the circuits. The ternary logic circuits using graphene nanoribbon transistors (GNRFETs) are presented in this work. The encoder circuit is proposed that helps to develop the complex arithmetic circuits like adder, subtractor, multiplier and so on. In this paper, adder circuit is considered as a complex circuit. The HSPICE simulator is used for ternary logic designs. The performance such as PDP and transistor count are investigated for proposed design and compared with the existing design. It is noticed that the proposed design improved the PDP up to 24% over the existing design. Furthermore, the proposed adder is designed using only 87 transistors, whereas the existing design uses 108 transistors. Hence, the area can also be improved in the proposed design technology.