Multi Gigahertz digital test challenges and techniques

The clock frequency of high performance VLSIs has exceeded 2 GHz. Over the years, aggressive scaling of CMOS process technology has resulted in a 30% annual performance improvement for digital circuits. However, tester speed has improved by only 12% every year. This paper discusses various test methodologies being used to cope with this speed disparity. These include: very low voltage test techniques; DFT structure incorporation; low frequency test modes; and dynamic CMOS implementations with integrated test mode structures.