A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology

In this article, we present a 4.13-GHz ultrahigh-speed (UHS) pseudo two-port SRAM for high-performance computing (HPC) in 4-nm FinFET technology. By applying the bitline (BL) charge time reduction (BLCTR) with clamped BL discharge (CBLD) scheme that improves BL charge and write time, the flying word-line (WL) architecture that enhances WL enable time, and the dual address pumping (DAP) architecture with flip-flop that reduces read and write switching time and address latching time, the proposed pseudo two-port SRAM demonstrates a UHS performance with a 4.13-GHz operating speed. A test-chip using the proposed scheme and architecture is fabricated in Samsung 4 nm FinFET technology and demonstrates UHS pseudo two-port 32-Kb SRAM operating at 4.13 GHz under 0.85 V and 100 c conditions.