An Optimized Vector Digital Signal Processor for 5G Achieving 0.3ms Channel Estimation time for 8RX 100MHz Bandwidth

In this paper, a parallel computing solution has been proposed to improve the timing of channel estimation (CE) in 5G applications. By utilizing the parallelism scheme of the digital signal processor with the Single Instruction Multiple Data (SIMD) architecture, the total computation time is drastically reduced to O.3ms instead of over 8.5ms with a scalar non-SIMD architecture based on the same hardware platform with the proposed SIMD vDSP, and both are at the same 5OOMHz operating frequency. Performance comparisons have been conducted to highlight the efficiency of the parallelism scheme with SIMD. Channel estimation schemes including least squared (LS), interpolation, and noise calculation have been implemented with the proposed parallel computing architecture for demonstration.